The present invention relates generally to semiconductor devices, and more specifically, relates to a method and system for forming source regions in memory devices.
Memory devices are widely used today for storing information for various application. Basic memory devices are typically structured in a column/row (bit-line/word-line) configuration. The data at each node may be stored and managed by a pair of transistor. One transistor might perform the function of control and the other might perform the function of data storage. One common type of memory device is a FLASH/EEPROM (Electrically Erasable and Programmable Read Only Memory). FLASH/EEPROMs can be accessed, read, written, and erased at speeds comparable to traditional RAM (Random Access Memory). They do not have the long access times of mechanical data storage (hard-media drives and soft-media drives). FLASH/EEPROMs also have an advantage in that they do not typically loose their data upon loss of power.
Typical FLASH/EEPROM fabrication processing creates structures that might have data retention problems. If the path between the floating gate (data storage) and the source is not sufficiently insulated, current leakage will occur. This current leakage will eventually reduce the potential of an “ON” floating gate, until it is no longer recognized as “ON” (i.e. the voltage has dropped below the threshold voltage).
One fabrication step in particular has been identified as a typical source of damage to the insulating oxides. This fabrication sequence occurs when the source well/region is implanted. Even with several well-known options for sequencing the ion implantation, it is difficult to avoid causing damage to the coupling oxide or the spacer oxide. The resultant damage creates leakage paths between the floating gate and source region, thereby degrading the data retention capability of the memory device.
What is needed is an efficient method for implanting the source region while not creating current leakage paths in the adjoining oxide areas.